This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-148413, filed May 27, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a data processing apparatus and a bus control method therefor, and, more particularly, to a data processing apparatus which deals with various kinds of data, such as audio/video data, other data and programs, and a bus control method for the apparatus.
Recently, as the computer technology is advancing, various types of digital information devices, such as a multimedia-handling personal computer, set-top box, digital TV and game machine, have been developed. There has been a demand for a capability to handle various kinds of media, such as a broadcasting medium, communication medium and storage medium, in digital information devices of this type.
Accordingly, people are demanding that personal computers should be provided with an ability to deal with AV (Audio/Video) stream data that needs real-time processing in addition to functions for processing ordinary programs. For consumer AV machines, such as a set-top box, digital TV and game machine, there has been a demand for a function to cope with software-controlled interactive title playback or the like, computer data, i.e., other data than A/V stream data, and programs is requested.
Because the internal buses in conventional computers handle an AV stream and computer data as the same type, however, they are inadequate to feed AV streams that demand highly real-time processing. When traffic of computer data becomes suddenly heavy while AV data and computer data are flowing on the bus at the sa me time (e.g., at the time of printing or accessing a file), for example, the AV data brings about a significant transfer delay. This is because AV data and computer data are not distinguished from each other on the internal bus, so that it is not possible to perform a process of letting AV data which needs real-time processing flow first by priority.
Further, since the architectures of conventional computer machines have a difficulty in guaranteeing the latency of data transfer, they require that a huge buffer for guaranteeing the latency be provided in an AV device or the like which is to be connected to the internal bus. In a case of handling streams of a variable bit rate, such as DVD titles, it was necessary to install a large buffer so that the buffer on a reception-side device would not overflow even at the maximum transfer rate. This requirement is a big factor to increase the cost.
Furthermore, if priority is given only to the transfer of AV data, when an event which needs fast processing occurs, a process for that event may be delayed.
Conventional AV machines physically accomplish peer-to-peer connection of devices that handle AV streams by connecting a plurality of devices in the processing order of the AV streams. Therefore, AV streams are not basically input to a CPU. The recent appearance of media (piper media) which has AV streams and interactive commands integrated demands that a CPU should process streams. This makes the present physical peer-to-peer connection of devices difficult, and studies on bus connection have started.
Accordingly, it is an object of the present invention to provide a data processing apparatus which can efficiently transfer stream data on an internal bus and is suitable for integration of AV streams and computer data, and a bus control method for the apparatus.
According to one aspect of the present invention, there is provided a data processing apparatus comprising an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time is defined as a transfer mode; a plurality of nodes connected to the internal bus and capable of transmitting/receiving stream data by using the band-guaranteed cycle; and means for causing a receiver node, which is receiving stream data transferred in the band-guaranteed cycle, to output a predetermined signal on the internal bus, thereby causing a sender node, which is transmitting the stream data in the band-guaranteed cycle, to stop transmitting the stream data.
In the data processing apparatus, the sender node which has stopped transmitting the stream data may restart transmission of stream data in the band-guaranteed cycle in a next cycle time.
In the data processing apparatus, the internal bus may include a signal line for indicating an end of a bus cycle which is currently being executed, and the receiver node which is receiving stream data transferred in the band-guaranteed cycle may make the signal line active to thereby stop transmission of stream data from the sender node.
In the data processing apparatus, the receiver node may comprise a reception buffer for temporarily storing stream data received over the internal bus and means for detecting if an amount of data stored in the reception buffer has exceeded a predetermined value, whereby when the amount of data stored in the reception buffer has exceeded the predetermined value, the receiver node outputs the predetermined signal on the internal bus.
In the data processing apparatus, the band- guaranteed cycle may be directly executed in a peer-to-peer mode between a sender node and a receiver node to which a same channel number is assigned.
According to another aspect of the present invention, there is provided a data processing apparatus comprising an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time is defined as a transfer mode; a plurality of nodes connected to the internal bus and capable of transmitting/receiving stream data by using the band-guaranteed cycle; means for assigning channel numbers respectively to the plurality of nodes connected to the internal bus such that data transfer in the band-guaranteed cycle is carried out in a peer-to-peer mode between nodes to which a same channel number is assigned; and means for causing a receiver node, which is receiving stream data transferred in the band-guaranteed cycle, to output a predetermined signal on the internal bus, thereby causing a sender node, which is transmitting the stream data in the band-guaranteed cycle, to stop transmitting the stream data.
According to a further aspect of the present invention, there is provided a data processing apparatus comprising an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time and an asynchronous transfer cycle for executing a transfer cycle in a period other than the reserved band in accordance with a bus access request from a bus master are defined as transfer modes; a plurality of nodes connected to the internal bus and capable of transmitting/receiving data by using the band-guaranteed cycle or the asynchronous transfer cycle; means for assigning channel numbers respectively to the plurality of nodes connected to the internal bus such that data transfer in the band-guaranteed cycle is carried out in a peer-to-peer mode between nodes to which a same channel number is assigned; and means for causing a receiver node, which is receiving stream data transferred in the band-guaranteed cycle, to output a predetermined signal on the internal bus, thereby causing a sender node, which is transmitting the stream data in the band-guaranteed cycle, to stop transmitting the stream data.
According to a still further aspect of the present invention, there is provided a data processing apparatus comprising an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time and an asynchronous transfer cycle for executing a transfer cycle in a period other than the reserved band in accordance with a bus access request from a bus master are defined as transfer modes; a plurality of nodes connected to the internal bus and capable of transmitting/receiving data by using the band-guaranteed cycle or the asynchronous transfer cycle; and means for giving a bus-using permission for the asynchronous transfer cycle to a sender node, which is transmitting stream data using the band-guaranteed cycle, in accordance with a bus access request from the sender node, wherein transmission of the stream data from the sender node to a receiver node can be executed in a period other than the reserved band.
In the data processing apparatus, the band-guaranteed cycle may be executed in a stream access mode for directly performing data transfer in a peer-to-peer mode between a sender node and a receiver node to which a same channel number is assigned, and when the sender node is granted a bus-using permission for the asynchronous transfer cycle, the sender node may transmit the stream data using the stream access mode in a period other than the reserved band by designating a sender node with a same channel number as the one used in the band-guaranteed cycle.
In the data processing apparatus, the sender node may comprise a transmission buffer for temporarily storing stream data to be transmitted in the band-guaranteed cycle and means for detecting if an amount of data stored in the transmission buffer has exceeded a predetermined value, whereby when the amount of data stored in the transmission buffer has exceeded the predetermined value, the sender node generates the bus access request.
According to a yet further aspect of the present invention, there is provided a data processing apparatus comprising an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time and an asynchronous transfer cycle for executing a transfer cycle in a period other than the reserved band in accordance with a bus access request from a bus master are defined as transfer modes; a plurality of nodes connected to the internal bus and capable of transmitting/receiving data by using the band-guaranteed cycle or the asynchronous transfer cycle; and control means for inserting the asynchronous transfer cycle in the reserved band cycle in the band-guaranteed cycle when the bus access request is generated from a node on the internal bus while the band-guaranteed cycle is being executed on the internal bus, and executing a remaining portion of the band-guaranteed cycle after completion of the asynchronous transfer cycle.
In the data processing apparatus, the control means may include means for determining whether or not the asynchronous transfer cycle in the reserved band cycle in the band-guaranteed cycle that is being executed and an asynchronous transfer cycle to be newly inserted can both be finished in a current cycle time when the bus access request is generated from a node on the internal bus while the band-guaranteed cycle is being executed on the internal bus, and may permit or inhibit reception of the bus access request based on a result of that determination.
According to a yet further aspect of the present invention, there is provided a data processing apparatus comprising an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined time to be used for data transfer for each cycle time is defined as a transfer mode; a plurality of nodes connected to the internal bus and capable of transmitting/receiving stream data by using the band-guaranteed cycle; and means for assigning channel numbers respectively to the plurality of nodes connected to the internal bus and outputting on the internal bus a channel number for which data transfer should be initiated, wherein data transfer in a peer-to-peer mode between a sender node and a receiver node to which the channel number output on the internal bus is assigned.
According to a still further aspect of the present invention, there is provided a bus control method adapted for use in an apparatus having an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time is defined as a transfer mode, which method comprises the steps of causing a receiver node, which is receiving stream data transferred in the band-guaranteed cycle, to output a predetermined signal on the internal bus; and causing a sender node, which is transmitting the stream data in the band-guaranteed cycle, to stop transmitting the stream data.
According to a still further aspect of the present invention, there is provided a bus control method adapted for use in an apparatus having an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time and an asynchronous transfer cycle for executing a transfer cycle in a period other than the reserved band in accordance with a bus access request from a bus master are defined as transfer modes, which method comprises the steps of giving a bus-using permission for the asynchronous transfer cycle to a sender node, which is transmitting stream data using the band-guaranteed cycle, in accordance with a bus access request from the sender node; and allowing the sender node to execute the asynchronous transfer cycle so that the sender node can execute transmission of the stream data from the sender node to a receiver node in a period other than the reserved band.
According to a still yet further aspect of the present invention, there is provided a bus control method adapted for use in a data processing apparatus having an internal bus for which a band-guaranteed cycle in which stream data is transferable in a band-guaranteed state by assigning a predetermined reserved band for each cycle time and an asynchronous transfer cycle for executing a transfer cycle in a period other than the reserved band in accordance with a bus access request from a bus master are defined as transfer modes, which method comprises the steps of inserting the asynchronous transfer cycle in the reserved band cycle in the band-guaranteed cycle when the bus access request is generated from a node on the internal bus while the band-guaranteed cycle is being executed on the internal bus; and executing a remaining portion of the band-guaranteed cycle after completion of the asynchronous transfer cycle.